1. Field of the Invention
The present invention relates to a logic circuit using a bipolar transistor and a MOS transistor and, more particularly, to a Bi-CMOS logic circuit in which a bipolar transistor and a CMOS element are formed on the same semiconductor substrate.
2. Description of the Related Art
The basic arrangement of an ECL logic circuit using a conventional bipolar transistor is shown in FIG. 1. Complementary inputs IN and IN are input to an emitter-coupled differential circuit constituted by npn bipolar transistors Q.sub.1 and Q.sub.2. In this case, when the input IN is a high-potential signal, the transistor Q.sub.1 is turned on, and the transistor Q.sub.2 is turned off, thereby flowing a current I.sub.1 through the transistor Q.sub.1. Therefore, the output potential of the transistor Q.sub.1 becomes V.sub.CC -I.sub.1 R, where R is the resistance value of resistor R.sub.1 and the output potential of the transistor Q.sub.2 becomes VCC. It should be noted that R is also the resistance value of resistor R.sub.2. The output potentials V.sub.CC -I.sub.1 R and V.sub.CC are level-shifted to V.sub.CC -I.sub.1 R -V.sub.f and V.sub.CC -V.sub.f, respectively, by an emitter follower circuit constituted by npn transistors Q.sub.3 and Q.sub.4. The voltage V.sub.f is a base-emitter forward biasing voltage of each of the bipolar transistors Q.sub.3 and Q.sub.4.
In the above ECL logic circuit, bipolar transistors are unsaturated. When inequality I.sub.1 R&lt;V.sub.f is satisfied due to the transistors Q.sub.3 and Q.sub.4 of a level shift circuit, the unsaturation of the bipolar transistors is ensured. Therefore, the ECL logic circuit is a logic circuit system having a high-speed operation and a large operation margin of bipolar logic transistors.
The above conventional ECL logic circuit has a merit of a high-speed operation. However, when the load capacitances of the outputs OUT and OUT are large, the ECL logic circuit has a problem.
That is, when the potential of the output OUT is pulled up from a low potential to a high potential, since the load is charged by the bipolar transistor Q4, this charging is performed at a sufficiently high speed. However, when the potential of the output OUT is pulled down from the high potential to the low potential, the bipolar transistor Q.sub.4 is cut off, discharging is performed by only a constant current source I.sub.2. Therefore, when the load capacitance is large, the speed of the pull-up operation is higher than that of the pull-down operation, and the operation speed of the whole circuit is decreased.
When the value of constant current sources I.sub.2 and I.sub.3 is increased to compensate for this drawback, the operation speed is not decreased, but power consumption in unit gate is increased. Since the ECL logic circuit generally has power consumption larger than that of a CMOS element or other bipolar logic circuits, a countermeasure for increasing the capacity of the constant current source cannot easily be employed.